Serial Eeprom Interface; Bbus Interface; Pwm Analog Outputs - GE MAC 5000 Service Manual
Resting ecg analysis system
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Also See for MAC 5000:
- Operator's manual (229 pages) ,
- Field service manual (160 pages) ,
- Operator's manual (258 pages)
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Serial EEPROM Interface
BBus Interface
PWM Analog Outputs
2-24
Equipment Overview: Theory of Operation
A special test mode is provided to allow testing of the thermal print head.
In test mode, print head power is disabled and the strobe signal is driven
continuously. This allows individual print dots to be driven with a small
test current via a current source (Q107, R319, Z100) enabled by a level
shifter (Q106, R318) driven from a ATMEL GPIO line. Half of the
resulting printhead voltage drop (divider R320/321) may be measured to
either determine the dot's resistance or at least determine if the dot is
open.
A standard four-wire SPI interface is provided for connection to a serial
EEPROM memory (CFGMEM). The ATMEL exchanges a byte of data
with the EEPROM by writing a value to the interface register. Data is
clocked at 4MHz; quickly enough that no interrupt support is required.
The ATMEL CPU polls a ready bit to determine when the transfer is
complete.
There are several I/O functions poorly suited to direct control by the
ATEML CPU, whether for reasons of software complexity or power
consumption. These I/O functions are provided by three 68HC705
microcontrollers placed strategically around the board (Moe, Larry and
Shemp). Each of these three microcontrollers must communicate with
the ATMEL CPU. BBus is a simple 1-wire point-to-point interface
designed specifically for this purpose. The FPGA provides a single BBus
transceiver and a 3-way bidirectional multiplexer to attach the three
BBus microcontrollers. For more Bbus information see the
microcontroller firmware source files. From the programmer's
standpoint, BBus operates like SPI, where each transaction exchanges a
single byte between the host and peripheral.
Four PWM channels are provided for the generation of analog outputs.
Three of the outputs are available on the Analog I/O connector; the
fourth is available internally for future use (if any). One of the PWM
channels provides 12-bit resolution at 6KHz cycle rate; the other three
provide 8-bit resolution at 96KHz cycle rate. The ATMEL CPU simply
writes the desired value into a PWM data register and the output duty
cycle changes on the next PWM cycle. External analog circuitry converts
the PWM logic signals to smooth analog voltages. The 12-bit PWM
channel is intended for ECG output and produces a swing of +10 to -10V.
The two 8-bit channels provide a unipolar 10V output. Regardless of the
resolution or swing range of each PWM channel, the FPGA treats the
data value as a signed 16-bit number representing a voltage from +10V
(0x7fff) to -10V(0x8000). Logic in each PWM channel ensures that the
closest possible voltage is generated for each data value (ex. 0x8000 on
an 8-bit channel produces zero volts output).
MAC™ 5000 resting ECG analysis system
2024917-010
Revision B
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